Adding Pads in Design Architect – IC
1.
Setting the Working Directory
2.
Invoking Design Architect - IC
3.
Generating a Symbol for Core Logic
5.
Adding Symbol to New Schematic
6.
Binding The Symbol With its IC Layout
11.
Creating The Final Cell Layout
14.
Routing the pads to the core
Pads are necessary to provide a larger surface area for the packaging tools, prevent electrostatics discharge and provide a generally more robust I/O interface.
Pads can be added in IC station or Design Architect – IC. Adding pads in Design Architect – IC automates the process and makes life easier for the chip designer
1. Setting the Working Directory
From the UNIX terminal, navigate to your original working directory, where the edf file was created as well as the eddm. In this case the directory is.
/hds_projects/TUTORIAL/TUTORIAL_lib/hdl
You may have a slightly different directory; however the hdl folder should
be the same.
Set this as the working directory using the “swd” command.
2. Invoking Design Architect - IC
In this case the pads will be
added to our design in Design Architect – IC.
Invoke Design Architect – IC from the working directory using the
command.
adk_daic
3. Generating a Symbol for Core Logic
You need to generate a symbol for each piece of core logic (component) that you want to use. You will also need a completed IC layout for each component for which you have a symbol.
Open the schematic for the layout you created in IC – Station. In this case it should be called “xnor2”
Use the command Miscellaneous -> Generate Symbol to generate a new symbol of your design. Make sure you click “Yes” on "Replace existing?" Leave all other options default. The symbol should appear as below.
Check and save the symbol. Close the schematic and newly generated symbol.
Now open a new
schematic using.
File -> Open -> Schematic
Change the component name to "FINAL.” The new empty sheet entitled sheet1 should open.
Note: Make absolutely sure that the file is created as $WGD_DA/FINAL.
5. Adding Symbol to New Schematic
On the right hand palette click
When prompted to choose symbol,
choose the symbol we have just created above.
Drop this component on the newly created blank sheet.
6. Binding The Symbol With its IC Layout
You need to add the “phy_comp” property to the symbol, so that the symbol can be identified with its corresponding physical layout.
Right click on the symbol that you have just added to the sheet. Choose properties -> add from the right click menu.
The value of phy_comp needs to be the name of the IC cell
layout that you created, also make sure that the property type is set to “String.”
The completed form should mirror that shown below. OK the form.
Perform a File -> Check -> Schematic. Ignore the unconnected pin warnings. Save the schematic.
In the ADK Library menu choose the pads to use from the appropriate library for your technology. Based on the technology, there may be different types of pads available. You can only use one set of technology pads and it must agree with the technology of your design. In this case, choose AMI 0.5. Wire the diagram together so it looks identical to that shown below.
Note: Notice the names PIN1, PIN2... ext. These names designate where in the padframe the pads will be placed, and must be changed from the original values of PADOUT1, PADINC1, PADGND, and ext. Since it is a 40 pin tiny chip pad frame, you can choose any value from PIN1 to PIN40; however values should be chosen based on efficient geometry. This means choose a pad closest to your input or output.
**Important: If
these pads are not labeled correctly the pads will not generate!
Save your design and quit design architect.
Make the design view points for the final schematic.
adk_dve FINAL
Invoke IC Station Using the Following Command
adk_ic
11. Creating The Final Cell Layout
Click the following menu item.
File -> Cell -> Create
Fill in the new
cell properties as follows
Cell name: FINAL_CELL
Attach library: $ADK/technology/ic/ami05
Process: $ADK/technology/ic/ami05
Rules: $ADK/technology/ic/ami05.rules
Angle mode: 45
Cell Type: Block
To link the
generated eddm Schematic Viewpoint with the newly
created Cell, click on “With connectivity.”
Using the browse
button, navigate through until you choose the correct eddm
schematic i.e. FINAL.
Double click FINAL; you should see several viewpoint options. Choose “layout” as the viewpoint by single clicking it.
Select “Logic
Loading Options” and choose “flat.”
Your window
should appear identical to the following.
Go to the ADK
Edit palette menu and click on Open to open the logic source window.
You should see
your schematic in a new window.
Select the
“XNOR2” symbol from the schematic window.
The symbol should now be highlighted.
Next click on “Inst”
on the “DLA Logic” palette.
Now click on the empty cell to place your symbol.
Note: Any cell you place in this manner must have a defined “phy_comp” property.
**Important – The cell you have just placed may not be visible until you change
the zoom. Choose View ->All.
In order to generate the Padframe go to
ADK -> Generate
Padframe -> AMI 0.5
This should bring up a generated padframe,
your cell should now look as below.
Note: If you do not have the 5 pads in your padframe, you probably did not label the pads correctly in Design Architect – IC.
14. Routing the pads to the core
After finalizing the placement of the core logic, you can route the pads to the core. You can do this manually or automatically.
To autoroute, click on “P&R” on the ADK Edit palette menu to bring up the Place & Route palette menu. Then click on “All” under “Autorout.”
On the prompt-bar that appears click Options and unselect “Expand Channels” from the menu. Click “OK” on the menu and prompt-bar to autoroute the pads.
Note: If you do not unselect “Expand Channels” the router may move the placement of the pads.
Now take a look at the final layout and fix any problems. Your final layout will look like the one shown below.
The final layout should be checked for design rule violations.
This can be done in the same way you checked your cell layout using Check in the “ICrules” palette with one exception. When you check the entire layout your will find some DRC errors in the pad frame as well as any DRC errors that still exist in the cell layout. The pad frame errors are inconsequential and are results of using an optional set of design rules. Focus on the design rules that exist independent of the pad frame by excluding certain cells from the DRC.
Select “Check” from the “ICrules” palette. Click on options in the resulting prompt bar,
and enter the following under “Exclude Cell”: PadOut, PadGnd, PadVdd and
PadInC.
If you did a DRC on your core logic, you can also exclude that from the checks. The form should look as shown below.
Once you have completed the DRC check and receive no
errors you may save and close your design.