Creating an Automated Layout Using IC - Station
1. Setting the
Working Directory
10. Comparing the Schematic and the Layout Using LVS
There are several tools in IC –
station to minimize the design time.
Your design can be placed, routed and optimized by the cad tools. This is especially helpful for large designs.
1. Setting the Working Directory
From the UNIX
terminal, navigate to the directory where your edf file is located. In this case the edf file was created in the
projects hdl directory.
/hds_projects/TUTORIAL/TUTORIAL_lib/hdl
Set this as
the working directory using the “swd”
command
Open IC –
Station from this working directory using
adk_ic
File -> Cell -> Create
Fill in the new cell
properties as follows
Cell name: xnor2
Attach library: $ADK/technology/ic/ami05
Process: $ADK/technology/ic/ami05
Rules: $ADK/technology/ic/ami05.rules
Angle mode: 45
Cell Type: Block
To link the
generated eddm Schematic Viewpoint with the newly created Cell, click on “With
connectivity.”
Using the browse
button, navigate through until you choose the correct eddm schematic i.e. XNOR2.
Double click XNOR2; you should see several viewpoint options. Choose “sdl” as the viewpoint by single clicking it.
Select “Logic
Loading Options” and choose “flat.”
Your window should
appear identical to the following.
Click “ok”
to generate the new cell.
To check if
the logic was generated properly navigate to the “ADK Edit” menu on the right
hand palette.
Once you are
there click the “Open” button to the
right of “Logic.”
The logic
should open and show you the following schematic view.
Note: If the
logic does not open properly it is probably due an incorrect working
directory.
Make sure
your working directory is the same as your .do file, and your .edf file.
On
the right hand palette navigate to the Place
& Route menu, this is done by clicking on Place & Route or P &
R.
From the Place and Route menu click on “Autofp.” In the “Autofloorplan
Options” dialog box, allow all options to default simply by clicking on “OK.”
The
floor plan should appear as below.
Note: If the
smaller green square is not in the center of the cell, the logic is not
correct. If the logic is not correct,
exit the cell and go back and start another cell.
In the “Place
& Route palette,” choose “StdCel” under “Autoplc.”
Click on “OK” in the dialog box.
You should
see individual cells placed within the floorplan boxes. Cell locations are
determined by their interconnectivity.
Cells which
share connections are placed near one another.
In this case we have only a single cell.
Note: If
you’d like to look inside the cells to see the transistor-level layout, select Setup
-> IC then from the menu select “Peek
on View.”
Then you can choose View -> Area to select the area to view.
Choose “Ports” under “Autoplc” to place ports. When prompted with the “Auto Ports” menu click “OK”
to select the default options. You will
see lightly shaded blue or purple areas along the bars at the edge of the
layout. These are the ports to your
design.
Now, from
the “Autorout” section of the “Place
& Route” palette select All, and accept
the defaults in the dialog box. This should route all connections in our cell.
You will see
the cell rows move apart and additional metal runs appear in the channels
between rows. Depending on the size of the design, auto routing may take
several minutes.
Several
small overflows may still exist. These small overflows may not be viewable on a
zoomed out design. To select all overflows in the design use the keyboard
command “check over.” In the form window that appears select “All” and “OK”
the form. Next, from the Place & Route palette, select “Overflw” under “Autorout”. If the response “An object of type Overflow must be selected” appears
in the status block, there are no overflows to route. Otherwise, the overflows
should be routed (i.e. you need to find a way to round the metal or poly from
one unconnected point – overflow – to the other).
A layout compactor
is available which compresses the design to a smaller area. To take advantage of this tool, from the “PR
Edit” section of the “Place &
Route” palette, select “Compct.”
We want to compact
in both the horizontal and vertical dimensions, so do this twice: once down and
then again in the left direction.
Note: Do not do this
more than once along a given axis. Not only does it rarely result in
improvement, it can lead to layout errors in some versions of the compactor.
The picture below is
a compressed version of the original.
From the Session
palette select “ICrules,” then select “Check” from the “ICrules” palette. You can get back to
that palette by hitting the right mouse button in the palette box and selecting
root. A prompt box will appear at the lower left of the screen. Click on “OK” to proceed with the check.
When the check is
complete, design rule errors which exist in the layout will be reported in the
message bar at the bottom of the ICstation window. If the number of ‘results’
is not zero, then there are errors. The first one can be shown by selecting "First" in the palette. Then rest can be viewed by clicking
on "Next".
One common error is the bad port error. The
port layers metal1.port or metal2.port must be completely covered with the corresponding
metal e.g. the metal2 layer coming up
to the metal2.port layer must
completely cover the it, not just butt up against it. The tool does not do this so we must fix it
manually. Go back to the IC Palettes menu and select Easy Edit. Type “sho la p” in the window to bring up the Show Layer Palette dialog box. Select
layers metal1 and metal2 by holding down the ctrl key and clicking on the layer
and OK the dialog. The selected layers
will appear above the Easy Edit palette. Now, click on the layer you want and
select Shape. OK the dialog box that
appears and draw required shapes to fix all the DRC errors. Once you’re finished, run the design rule
check again.
10. Comparing the Schematic and the Layout Using LVS
Verify the layout for consistency with the transistor level
schematic of your design. Do this by returning to the main Session palette and selecting the ICtrace(M) (mask level LVS) option. Click on LVS in the ICtrace(M)
palette and in the form which appears, select the LVS viewpoint using the
Navigator button. For example, if your design is named “XNOR2” the LVS viewpoint can be found by navigating down into the “XNOR2” directory and selecting the “LVS” directory. Click on the Setup LVS button and in the form that
comes up change the following items and click OK
Fill in the form so that it mirrors the form shown below.
After you run LVS
check you can view the report by clicking.
Report -> LVS
A correct report
should have a check mark and smiley face.
If you do not have this you may need to go back over previous steps.
Save your design and
exit IC – Station
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