Creating a Design Using HDS Designer
1.
Starting HDL Designer 2003.3
3. Creating
an XNOR gate With VHDL
HDL Designer Series is a suite of tools that provide a complete solution for creating, analyzing, documenting, and managing complex VHDL and Verilog designs for ASICs and FPGAs. HDL designer is covered in much greater depth in the Programmable Logic course. In this tutorial we will see how to enter a simple circuit using the VHDL editor.
1. Starting HDL Designer 2003.3
a) Enter “source hds.csh” at the UNIX command prompt. You should get the following options.
b} Enter 1 for 2003.3
c) Enter hds to start HDL Designer 2003.3
When the welcome dialog box appears (as shown below). Click on “create a new project” radio button. Then click “OK.”
The next screen should appear as below.
If it does not select the File -> New Project pull down command.
Enter the name of the project. Here I chose “TUTORIAL” as the project name.
Enter the directory where it will be created (Make sure it is created within your working area - /disk2/acc/xxx, where xxx is your HOME directory. In this case the initials cla represents the user name. You may also create subdirectories within your working area.
Click NEXT.
Make sure the “create new design files” radio button is selected.
In the next screen shown below; the type of file we will create is specified. Notice how we could create a graphical view such as a flow chart or state machine. We could also select a “registered view” such as a c++ to describe our system. In this case we will select the “combined” option. The combined option is a vhdl file, which includes both architecture and entity. The architecture and entity will be discussed further in this tutorial.
Make sure the VHDL 93 radio button is selected. This enables the VHDL 93 syntax.
Click the next button
In the next screen you are prompted to specify the name of the VHDL entity and Architecture you will create.
Click the finish button.
The VHDL Architecture and Entity templates should appear in a text document.
3. Creating an XNOR gate With VHDL
Fill in the necessary text so that your file is identical to the file shown below.
Lines 10-16 shown below select the VHDL libraries we will use for our design. These statements are similar to the c++ # include. These libraries contain basic logic components as well as predefined logic “types” so we don’t have to reinvent the wheel.
Lines 20-24 represent the “Entity” of the XNOR gate. An entity is a description of the inputs and outputs of the design you are creating. Inputs and outputs can be bussed together or defined separately. In this case we are creating an XNOR with two inputs and one output. The entity name we chose is XNOR2.
Lines 28-38 represent the “architecture of the “XNOR2” Entity. This type of description is known as a behavioral description. Lines 34-36 describe the behavior of this component. This is why we chose the architecture name “behavioral_xnor.” Another architectural style; not included here, is known as structural. With the structural statement, we define the architecture with a more direct approach; almost as if we were physically wiring together smaller components.
Save the design by clicking the save icon, or file -> save.
Note: The save
feature also checks for syntax errors and will not save your design until you
have eliminated all errors.
If errors exist fix them and try the save button again.
Leave the text editor screen and go to the main HDS screen.
The TASKS window should be docked on the right of the screen. If not Click on
Tasks => Tasks and Templates
The tasks window should now be docked on the left hand side of the screen. All the available downstream applications are displayed. We will be using Modelsim for simulation.
Double click the modelsim icon “Generate” in the right hand task window to generate a VHDL design object from the VHDL source text file.
The Log Window will display the results - correct any errors detected.
Choose “Modelsim Compile” to a simulation object, which prepares the files for simulation.
The Log Window will display the results - correct any errors detected
Click here to continue to the Simulation Using Modelsim Tutorial