Creating a Full Custom IC–Station Layout
1.
Setting the Working Directory
4.
Setting up the Layer Palette
7.
Determining the Stick Diagram
8.
Creating an NMOS Transistor
13.
Adding Power and Ground Rails
14.
Adding Transistor Bulk Connections
In this tutorial you will learn how to use Mentor Graphics IC-Station to construct a full custom
layout of an inverter, i.e. a hand crafted creation of an IC cell. You will create the artwork that specifies
transistor layouts and their interconnection. You will also verify that there
are no design rule errors in the final layout. You can use what is illustrated
in this lab to construct CMOS logic gates.
It
is assumed that prior to this tutorial you created the schematic of the
inverter in Design Architect using the SDL's pMOS and nMOS transistors.
Also, that you ran the adk_dve
command on your inverter design to create the sdl view point:
adk_dve
your_design_name -technology ami05
1. Setting the Working Directory
From the UNIX terminal, navigate to the directory where you have
created your design viewpoint using adk_dve. This should be the same
location as your Design Architect Schematic.
In this case we have called the design “inv” and it should be located in your home directory,
i.e. just under your user name.
disk2/acc/xxx
Where “xxx”
represents your user name.
If you are not already in this directory, navigate to this
directory. Set this as the working
directory using the “swd” command.
Invoke IC station with the following command:
adk_ic
Click the following menu item.
File -> Cell -> Create
Fill in the new cell
properties as follows
Cell name: inverter
Attach library: $ADK/technology/ic/ami05
Process: $ADK/technology/ic/ami05
Rules: $ADK/technology/ic/ami05.rules
Angle mode: 45
Cell Type: Block
To link the
generated eddm Schematic Viewpoint with
the newly created Cell, click on “With connectivity.”
Using the browse
button, navigate through until you choose the correct eddm schematic i.e. inv.
Double click inv; you should see several viewpoint options. Choose sdl as the viewpoint by single clicking it.
Choose “Logic
Loading Options” and then select “Flat.”
Your window should
appear identical to the following.
4. Setting up the Layer Palette
One way to customize the layer palette is to use the menu option
Other->Layers->Append
to Layer Palette
Another way is to hold the mouse pointer onto the blank sheet and type
on the keyboard “sho la p.” In the dialog that opens, scroll down and
select the layers you want to draw with (p-well through metal3). You can select
these by clicking on p-well, then hold down shift and use the down-arrow to
select what you want. The image below shows the palette on the upper right with
several layers chosen, as well as the “Show Layer Palette.”
Let's make sure the grid is set up. Go to
Other->Window->Set Grid
Verify that the dialog box looks like the image below.
This will make all points you click snap to a one lambda grid.
Now turn on port names (they are invisible by default). Do “Setup->IC” and turn on "Port-Pin Name Display"(see image below) in the dialog that appears.
Under Setup->IC change the Port/Pin Name Display
to ON (this will display of ports
and pins).
7. Determining the Stick Diagram
8. Creating an NMOS Transistor
Now we will start drawing our first transistor, which will
be the NMOS transistor of the CMOS inverter. From the schematic we know that
this transistor has a channel width of 5λ.
The width of the transistor will correspond to the width of the active area. We will select the n-diffusion layer and draw a rectangular active area to define the transistor.
Select “active” layer from the
upper right hand layer palette.
Select “shape” from the “ADK Edit” palette
You are now in rectangle mode. Select the first corner of rectangle in the layout window (you may select any point within the window but try to select a point close to the origin),
click once, and then move the mouse cursor to the opposite corner. While observing the Cursor position readout, draw a box that is 13λ horizontal and 5λ vertical.
All units are in Lambda by default. The grid should be set
to snap to ½ λ increments.
The second step
is to draw the gate. We will use a vertical polysilicon rectangle to create the
channel.
Note that the length of the transistor channel will be determined by the width of this poly rectangle.
Select the “poly” layer from the “layer
palette.”
The ami05 design rules tell us that poly must be at least (2 Lambda) from edge of the diffusion.
Select “shape” and draw the poly rectangle 2λ horizontal and 9λ vertical. The 2λ dimension comes from the length of the channel as indicated in our schematic. The other dimension requires a 5λ channel width plus the 2λ overlap required on each edge, thus totaling 9λ.
The poly shape should be centered as shown below.
The next step is to make the active contacts. These contacts will provide access to the drain and source regions of the NMOS transistor.
Select the “Contact to Active” layer.
Create a square with a width and height of 2λ, as described by the design rules. Center the square as much as possible in the active region,
but make sure it is at least 2λ from the poly layer. It should appear similar to below.
Select the contact by single clicking upon it.
Now select the “copy” button from the right hand menu palette.
Drag the mouse pointer into the sheet and place the new contact symmetrically opposite the first, as shown below.
Select the “metal1” layer from the layer palette.
Draw two metal squares surrounding the active contacts by at least 1λ in all directions as specified by the design rules.
Note: Each diffusion area of each transistor must be selected as being of n-type or p-type. The green active region does not specify the type of the transistor;
it merely indicates the desired size of the transistor. The transistor type is literally defined by the special mask layer called n-select (p-select).
An “n-plus_select” layer results in an NMOS, and similarly a “p_plus_select” in a PMOS.
Select the “n-select” layer from the palette.
Draw an outer ring surrounding the active layer by at least 2λ in all directions as defined by the design rules. You should now have the image below.
You have now created one NMOS transistor. Actually what you have created is this.
The n+ select regions and a gate;
which are surrounded by a huge tub of p-substrate (blank empty space is
p-substrate by default).
The PMOS is so alike to the NMOS we can start by copying everything we have done.
Select everything by drawing a box around everything. Then do a right-mouse-button Copy (copy) and copy everything.
Place the copied transistor above
the original transistor
Unselect all (F2) and then select the top transistor's n-select. With that selected do Objects->Change->Layer (cha la) and change it to p-select.
Unselect all and view all to make
sure it looks like the following figure. You now have an NMOS on the bottom and
a PMOS on the top.
You now have the following.
Notice that our second transistor is P+ surrounded by p-substrate.
To fix this problem select “n-well” from the palette.
Draw a large n-well surrounding the p+ layer by at least 6λ in all directions, as specified in the design
rules.
Your figure should no resemble the image below.
We have now corrected our design and have two functional transistors,
as shown below.
Wire together the two drains of the circuit using metal1. Make sure that it is at least 3λ to satisfy design rules.
Note: instead of using “shape” to create the shape you can instead use “path.” Click the options button, and change the width to 3λ.
Connect the two drains of the circuit.
Now select the “poly” layer, and change the width to 2λ; wire together the two gates of the circuit. The circuit should now appear as below.
11. Creating the
To create input port we must first jump to the “metal2” layer and then create a port.
To do this; extend the “poly” out to the left in a 5λ by 5λ square.
Next place a 2λ by 2λ “contact to poly” in the center of the poly square.
Surround the “contact to poly” square by metal1. “Metal1” must overlap the poly by at least 1λ.
Next place a “via” (connection between “metal1” and “metal2”) at least 2λ from the “contact to poly” square.
Surround this “via”
with “metal1” and “metal2” by at least 1λ. The resulting figure should appear as the
image below.
To make the in port, select the metal2 layer then execute Objects->Make->Port
(mak po). In the
lower-left dialog, set it to the following:
Port type: signal
Direction: in
Port name: IN
Click OK and the name of the port (in) should appear.
If not, go back to instructions at the top of the tutorial to turn on port/pin
names and then redisplay.
The name of the port should appear on the port as below.
12. Creating the
To create the output port we only need to jump from metal1 to metal2.
Draw a 4λ by 4λ metal1 layer to the right of the metal1 output path.
Draw a 4λ by 4λ metal2 layer covering the metal1 layer.
Draw a 2λ by 2λ via in the center of the other two layers.
Finally select the metal2 layer and execute Objects->Make->Port
(mak po). In the
lower-left dialog, set it to the following:
Port type: signal
Direction: out
Port name: Out
Both input and output ports have now been added.
13. Adding Power and Ground Rails
Add larger metal1 layers both above the PMOS and below the NMOS. These layers are also known as power and ground rails respectively.
Connect metal1 paths between each rail and the source of each transistor as shown below.
Now make the power rail a port by
selecting Objects->Make->Port (mak po). Choose the following options.
Port type: power
Direction: in
Port name: VDD
Repeat the same action with the ground rail; this time with the following options.
Port type: power
Direction: out
Port name: GND
The VDD and GND labels should now appear.
14. Adding Transistor
Bulk Connections
Type the keyboard command “nwc” for nwell_contact . Place the contact over the power rail.
Type the keyboard command “pwc” for pwell_contact. Place the contact over the ground rail.
Click DRC->Check from the right hand palette. Click “ok” to choose default options.
If there are DRC errors you can view them one at a time by clicking DRC -> First, and then DRC -> Next for each additional error.
Fix each error according to the known design rules.
Note: The design rule errors are written in text at the bottom of
the window. The expected size in λ is
also given.
LVS check compares the layout you made in
IC-Station with the schematic created in Design Architect.
Navigate the right hand palette to the “IC Palettes” menu.
From IC Palettes click ICtrace (m) then click “LVS.”
Fill out the menu so it looks as
follows. Choose the lvs viewpoint as the “Source Name.”
Note: choosing lvs viewpoint may require you to close the current logic if any is open. To do this select Logic -> Close, from the ICTrace (m) menu.
Press “OK” when you are done filling in the sheet.
To view the results click “Report -> LVS” from the ICTrace(m) menu.
If the results are correct check mark and smiley face logo should appear.
You have completed the tutorial and may now exit IC-Station.