Schematic Driven Layout Using IC - Station
1.
Setting the Working Directory
4.
Auto-Instantiating Components
The IC station family represents a range of tools for composite IC design whose flexibility adapts them to almost any IC design process. IC station supports polygon, symbolic, cell, and block IC designs in combinations of unconstrained and connectivity-based editing configurations. Continuous integration places all tools on a single database, eliminating conversions and translations among tools for cell and block design, automatic placement and routing, floor-planning, compaction, and verification. This environment enables composite design: the mixture of IC design styles on a single die.
The IC station tools are built upon the Falcon Framework for Concurrent Design, making it a component of the Concurrent Design Environment. All IC Station configurations build upon the framework’s user interface, data modeling, and design management facilities to bring the engineer integrated seamless interaction among design tools. This integration enables the design engineer to choose the design technique and tool he/she needs for each section of his IC design. The Concurrent Design Environment encourages coordination among all IC design engineers and unites all engineering disciplines involved in bringing their electronic systems to market.
This tutorial will step you through the process of performing SDL in IC Station. Anything you already know about placing ports, cells, shapes and paths is still applicable. You will learn the additional functionality associated with SDL. You will layout your inverter that you created in DA lab. If you do not have the schematic capture of an inverter, draw it for this lab experiment.
1. Setting the Working Directory
From the UNIX terminal, navigate to the directory where you have
created your design viewpoint using adk_dve. This should be the same
location as your Design Architect Schematic.
In this case we have called the design “inv” and it should be located
in your home directory, i.e. just under your user name.
disk2/acc/xxx
Where “xxx” represents your
user name.
If you are not already in this directory, navigate to this
directory. Set this as the working
directory using the “swd” command.
If you have generated the necessary viewpoints in the previous tutorial then may invoke IC station with the following command:
adk_ic
If you have not generated viewpoints go back to the Creating the Design Viewpoint
tutorial.
At this point you should maximize the window and set up the environment
for easier use. Using the MGC->Setup,
select “Left Right Tiling” and leave
all other options default.
Click the following menu item.
File -> Cell -> Create
Fill in the new cell
properties as follows
Cell name: inv
Attach library: $ADK/technology/ic/ami05
Process: $ADK/technology/ic/ami05
Rules: $ADK/technology/ic/ami05.rules
Angle mode: 45
Cell Type: Block
To link the generated
eddm Schematic Viewpoint with the newly created Cell, click on “With
connectivity.”
Using the browse
button, navigate through until you choose the correct eddm schematic i.e. inv.
Double click inv; you should see several viewpoint options. Choose sdl as the viewpoint by single clicking it.
Your window should
appear identical to the following.
From the DLA Layout menu, you need to open your schematic sheet. Click
on the Open button to invoke it.
It should appear below your layout window if you set up the tiling as
previously instructed.
4. Auto-Instantiating Components
Now you can place the devices into your cell. You will use the
automatic placement method for this exercise. To do this, click on “AutoInst” on
the right hand palette menu.
At this point, the tools will locate devices that are of the same type
and have connectivity such that diffusion regions may be shared. The devices
will be automatically generated based on the length and width parameters
specified on the instances and placed into the open cell. Overflow lines (in
yellow) will show you the connectivity points in your circuit. As you wire the
circuit together, these overflows will disappear when you have made the correct
connections.
After clicking “AutoInst” move
the mouse pointer into the blank sheet.
Click once in the sheet so that the components are dropped in the
correct location.
Your sheet should now appear as below.
To move the devices, select one like any other cell. The only problem
is that the bulk of the transistor is also a pin and you probably have selected
this pin and not the instance. If that is the case, click on the device, again,
to highlight the entire device and then you will be able to move it.
Optionally, you can use the mouse to select an area that includes the device
you want to move and that will select the device (and the bulk) in one
operation.
Notice that when you select a device or a net it is also selected in
the schematic window. This cross-selection is very useful. Since you will have
the bulk selected, and since it's connected as a net, that net will be
highlighted. The individual devices will not be highlighted as you have
selected a merged device that really doesn't exist in your design. If you
select one of the gates, however, that device will be highlighted in your
schematic. Play around with selecting things for a moment to get a better feel
for how this all works.
You will have to place some polysilicon wires. First, show the layer
palette to make things easier. To do this operation, type “sho la p”
(this stands for "show layer palette" but is easier to type). Now,
while holding down the control key, click on the layers POLY and METAL1. If
you need to scroll down the window, release the control key before scrolling,
then hold it down again when clicking on the layers.
Now click on Path on the palette. You will
be prompted for a location. Before placing the path, click on the poly layer in
the layer palette at the upper right of the window. Now you will place a route
on the poly layer. Now click on the Options button on the prompt bar. You need
to change the width to 2 microns but leave everything else alone. Select the Keep Option Settings box and exit the dialog
box. The poly path is the red layer.
Wire the gate inputs with poly as shown below.
Note: Be sure to follow the design rules! Two micron minimum
width, three micron separation, etc.
Next select metal1 by clicking
on the metal1 layer in the layer
palette. Change the width to at least 3
microns, and connect the outputs, as shown in the blue layer below.
Again select Metal1 from the layer
palette and then select the shape from DLA Layout palette. Draw power and
ground rails next to pdiff and ndiff regions.
When you are done your layout will be similar to the one shown below.
Be sure to wire all the overflows. Also be sure to wire the correct
pins to the power and ground rails.
Once you have the gates wired together, you need to place the ports for
the inputs and outputs from your schematic. Before you can place ports, you
have to select the type of port you wish to use. Go to the Setup->SDL
pull-down menu to complete operation, Click on SDL Port Styles and then press the Setup button. You should then select
To place the ports, select the input and the output in your schematic
window. Then make the layout window active, again, and click on Port in the
DLA Layout palette menu.
One by one, you are prompted to move these ports to where you want
them. Then the port will be placed on is highlighted in the layout window to
make it easier to see which port is being placed.
From the main palette select Setup->IC and activate Port/pin Name Display On. This will show the port names
in the layout.
Next, select only the power (top) rail in your layout. With this shape
selected, use the Objects->Make->Port: menu to make this a port.
You will be prompted for the type (make it power) and for the port name (make it VDD). Leave the direction as in since the power will be
coming into this cell.
Do the same thing for the ground (bottom) rail but name it GND. Name the input and output port as well.
Now wire up the other ports. Since the signal ports are metal2, you
will need to get a connection from poly to metal1 and then to metal2 and for
the output, you'll have to go from metal1 to metal2 only. Fortunately, there
are some handy commands that have been scripted to help you accomplish this. To
access these, simply type them in the layout window.
pp: The
pc: The Poly Contact command will place a poly contact
with metal1 centered at the point you are pointing to with the mouse.
These commands make it easy to wire up your ports. Simply place the
poly contacts and vias as you need. The
resulting layout is shown below.
Finally, you will place diffusion contacts. There are two macros for
these, as well:
nwc: N-Well Contact command will let you drag an n-well
contact around and place it whenever necessary.
pwc: P-Well Contact command will let you drag a p-well
contact around and place it whenever necessary.
You should place an n-well contact on the VDD rail so that the
contact's top edge coincides with the top edge of the VDD rail.
The p-well contact should be placed on the Ground rail so that it's
bottom edge is coincident with the bottom edge of the rail.
Note: The N-Well Contact should touch the N-well.
See the image below for reference.
Now it is time to see if you pass DRC. Use the Drc menu on the DLA
Layout palette to do a Drc->Check.
Simply click OK on the prompt
bar and DRC will be performed. Fix all DRC errors, if you have any.
Click Here to Continue to Using MACH-TA for Simulating Digital Circuits