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Engineering
Science: 12.5%
Engineering Design: 87.5%
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Credits: |
3.0 (Fall Semester
Design-2004)
1.0 (Spring Semester Testing-2005) To be completed one month after
chips arrive from the foundry. |
|
2003-2005
Undergraduate Course Catalog Data: |
Principles of VLSI (Very
Large Scale Integration) systems design at the physical level. CMOS
circuit and logic design, CAD tools, CMOS system case studies.
Fundamentals of nanotechnology and MEMs (Micro Electro Mechanical
devices) Students exercise the whole development cycle of a VLSI
chip: design, layout, and testing. Design and layout will be
performed during Semester I. The chips will be fabricated off
campus, and returned during Semester II, when they will be tested by
the students. An IA grade will be given at the end of Semester I.
Prerequisite ECE612. 4 cr. |
|
Textbooks: |
Neil Weste and David
Harris, CMOS VLSI Design - A Circuits and Systems Perspective,
Addison Wesley, 2005.
Wayne
Wolf, FPGA Based System Design, Prentice Hall
2004.
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|
References |
Mentor Basic Training Manual (Design Automation Laboratory)
Mentor Manuals (Design Automation Laboratory).
On-Line Mentor Manuals (command
prompt>>mgc_acro)
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|
Instructor |
Dr. Andrzej Rucinski
tel. 862-1381 |
Kingsbury Hall - Room 104 andrzej.rucinski@unh.edu |
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Project
Coordinator |
Corey Allen |
Kingsbury Hall - Room 105F coreya@unh.edu
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COURSE CONTENT
Prerequisites by topic:
- Boolean algebra
- Principles of digital
logic
- Computer organization
- Basic circuit theory and
electronics
- Ability to use a
personal computer: word processing, graphics, and basic programming.
Note: ECE715
satisfies a course requirement in the ECE Departmental Design Experience
Rule.
Topics:
- CMOS technologies
- VLSI system design
principles
- Computer Aided Design
tools (Mentor Graphics suite)
- Technology Migration
(from FPGA into ASIC)
- Integrated circuits
manufacturing
- VLSI technologies
constraints
- VLSI testing
Course objectives and
philosophy
The basic purpose of this
course is to introduce senior and beginning graduate students in
electrical engineering to modern microsystem design with emphasis on
semi-custom and full-custom Very Large Scale Integration (VLSI). There are
four fundamentals determining this process: technologies, design
strategies, design tools, and implementation related limitations. The
course will address all these design aspects. The specific topics will
include: VLSI development tools, general design principles, system
hierarchy, design styles, specific "real world" considerations such as
interfacing techniques, delay, speed, power dissipation, noise, loading,
etc... The course will also stress report writing, documentation, and oral
communication skills. Much of the learning will occur independently in
the Design Automation Laboratory (DAL). Labs will be supported by
formal classroom presentations and by assistance in the lab.
Schedule for Fall and Spring Semester
During the fall semester the designs will be implemented, simulated,
and submitted for fabrication. The designs will be tested and
evaluated during the spring semester.
A grade of course continuing (IA) will be assigned
at the end of the fall semester. A final grade will be assigned at
the end of the spring semester upon completion of device testing .
There will be field
trip tour to the BAE Systems' fabrication facility
in Nashua, New Hampshire.
Note: The
fabricated devices should arrive back from
the foundry around the first of April, 2005.
COURSE INFRASTRUCTURE
Design content of the
course
The course satisfies a
design experience requirement of the Department of Electrical and Computer
Engineering. The rationale behind this statement stems from the following:
The student exercises the whole prototyping sequence of a VLSI
chip, from design entry, simulation, layout, post-layout simulation,
submission for fabrication, verification, and
testing.
Note: the ECE
Department requires team-oriented projects to satisfy its design
experience requirement.
VLSI project: The
Design of FPR System Components
BACKGROUND
: Over the past two years a fingerprint authentication device has been
in development. Thus far
a fully functional prototype has been developed.
This prototype consists of a Virtex2 FPGA and prototype board,
as well as an Authentec finger print scanner.
In order to complete this project however, the design must be
converted from the FPGA prototype, to a finalized ASIC.
Some parts of this project can be directly converted using
existing VHDL code, other pieces can not. Components which can
not be easily converted from FPGA to ASIC will be given as a project
option.
DESIGN SPECIFICATIONS
:The design has several distinctive modules. All modules and
specification can be found under projects
assignment options on this web site.
Each
design will be
completed by a team of one or two students. There are several sources
of information to assist students. They are located as the WEB site of
the course description. In addition, there are boundary scan materials
(books and student reports) on reserve in
the Kingsbury Library.
PROJECT ORGANIZATION
: The project
will be coordinated by a graduate student.
Each team has the following tasks to fulfill:
- Become familiar with boundary scan concepts;
- Write a description for the module you have chosen to design and implement;
- Create a schematic for your module using Design Architect;
- Simulate your design using Quicksim;
- Layout your design using IC station;
- Simulate and verify your design using the MAC timing analyzer.
-
Prepare the database files for
fabrication
-
Test the devices when returned from
the VLSI foundry
There will be
periodic meetings to coordinate the effort
and identify problems.
WEB usage:
A
email list and help file will be used to communicate course and design
information.
COURSE ORGANIZATION
Tentative
Lecture Schedule
| |
TOPICS |
Approx. Number of CLASSES |
| |
Course Overview |
1 |
| |
CMOS
Circuits |
2 |
| |
CAE Design Flow - DAL and
Design Strategies: Using Mentor Graphics |
1 |
| |
MOS
Transistor Theory |
3 |
| |
Layout
Design Rules, and Latchup |
2 |
| |
Logic
Design, Sizing, Complex Gates, Transmission Gates, Domino and Dynamic
Logic,, Timing, Metastable States, and I/O Structures |
8 |
| |
Circuit
Element Characterization, Capacitance, Delays, Cascaded Delays |
5 |
| |
CMOS
Fabrication and Field Trip |
2 |
| |
Design
Methodologies, PLA, FPGA, and Standard Cells |
2 |
| |
Testability and Yield
Issues |
2 |
Computer Usage:
-
Laboratory exercises
that require extensive usage of computers in all stages of
the development cycle (design entry,
simulation, programming, testing, and verification).
- Typed
design progress reports are required.
- Intensive testing and
verification procedures are required at the development stage and the
prototype evaluation stage.
Laboratory Projects
(including major items of equipment and instrumentation used):
Major Equipment (available in the Design Automation Laboratory)
- Sun/Mentor CAD workstations: SUN ULTRA Enterprise 450 server and SPARC stations
- Functional Test Station
- Oscilloscopes,
signal generators,
and logic analyzer.
Lab Schedule
|
TOPICS |
DUE DATE |
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|
|
|
LAB1. |
Introduction to DESIGN ARCHITECT and ACCUSIM
LAB |
Sept.
16 |
|
LAB2 |
Designing CMOS Circuits with DESIGN ARCHITECT and ACCUSIM LAB |
Sept.
23 |
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LAB3. |
IC STATION LAYOUT
LAB |
Sept.
30 |
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LAB4 |
IC
STATION SCHEMATIC DRIVEN LAYOUT LAB |
Oct. 14 |
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LAB5 |
Simulation with MACH Timing Analyzer |
Nov. 9 |
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|
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Design Schedule
| |
TOPICS |
DUE DATE |
WEIGHT |
| |
PROJECT PROPOSAL
(oral presentation in class and written report
- Senior Project Proposal) |
Sept. 23 |
10 |
| |
FIRST PROJECT REPORT (PDR)
(written report) |
Oct. 21 |
10 |
| |
SECOND PROJECT REPORT
(CDR) (written report) |
Nov.18 |
10 |
| |
FINAL PRESENTATION (FDR)
(individual student's demonstration, written report) |
Dec. 13 (reading day) |
20 |
| |
VLSI TESTING
(written report) |
April
2004 (tentative) |
10 |
Grading System
| |
WEIGHT |
| HOMEWORKS
and QUIZZES |
20 |
| LAB
EXERCISES |
20 |
| PROJECT
PROPOSAL |
10 |
| FIRST PROJECT
REPORT |
10 |
| SECOND
PROJECT REPORT |
10 |
| FINAL
PRESENTATION |
20 |
| VLSI TESTING |
10 |
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_______________________ |
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| TOTAL WEIGHT |
100 |
Note: Ten (10) points will be deducted from an
assignment's grade for each day it is late.
ABET category content is estimated by faculty member who prepared
this course description:
Engineering Science: 0.5 credits or 12.5%
Engineering Design: 3.5 credits or 87.5%
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