ECE 715/815

Introduction to VLSI

VLSI Project

2004, Fall Semester

Fingerprint Recognition SoC

Project Assignments

*Block Number)**	Name	Type	Team
3	Image memory	Dual port RAM	2
7	Temporary memory	RAM	2
4	Spatial filter coefficients memory	ROM	1
6	Shift register with feedback	Shift Register	2
13	Matched filter coefficients memory	ROM	1
11	Template memory	ROM	1
10a	Flash/ EEPROM parallel interface	Memory interface	2
5	2-D to 1-D coordinates converter	Image memory interface	2
5,10,12	Multipliers and adders	Arithmetic functions	2
5	Spatial filter	2-dimensional filter	2
			17

*) See the block diagram of the Fingerprint Recognition SoC

General Information

All project assignments are part of the fingerprint authenticator implemented in ASIC.

Target clock speed: 100 MHz

Representation of numbers:

- fixed point integer

- 2’s complement format wherever signed numbers are used

- complex numbers are 32 bit vectors (upper 16 bit correspond to a real part, and lower 16 to an imaginary part)

Synchronization:

- synchronous logic operates on a rising edge of the clock

- inputs are sampled on a rising edge of the clock

- outputs are updated on a rising edge of the clock

Contents of the report:

- assignment goal and desired design specifications

- research and trade off studies

- architecture design and design partitioning

- design process (block diagrams, schematics, calculations)

- simulation results and timing diagrams

- achieved design specifications

- conclusions

Image Memory (3)

The purpose of this assignment is to develop a dual port SRAM used by a fingerprint recognition system.

Table 1 Interface of Fingerprint Image Memory.

Input
ADDR_A	14 bit
ADDR_B	14 bit
DATA_IN_A	8 bit
OE_B*	1 bit
WE_A*	1 bit
Output
DATA_OUT_B	8 bit

The dual port architecture (see the picture on the right) has been chosen to simplify read and write procedures. The port A of the image memory is “write-only” and is used to write image data from a fingerprint sensor at a rate of about 4 kB/sec. The port B is “read-only” and is used to access the image data for the image matching algorithm. 14 bit address buses (m=14): ADDRA and ADDRB, allow for addressing 16384 memory locations (n=8 bit). It is enough to fit 128x128 pixels grayscale fingerprint image. The image data (through Data_in_A) is stored in the memory on a falling edge of WE_A*=1. The data is read from the memory on the falling edge of OE_B*. Simplified timing diagrams can be found in the Appendix.

Shift Register with Feedback (6)

The purpose of this assignment is to develop a shift register with feedback. The shift register was chosen to adjust slow data rate output of a spatial filter to the speed of a FFT core. The feedback loop is added to allow for overlapping of data sent to the FFT.

Table 2 Interface of Shift Register with Feedback.

Input
CLK	1 bit
IN	32 bit
Output
OUT	32 bit

The length of the register is 2048 points. Each point is 32 bits wide and corresponds to a complex number where upper 16 bits form a real part, and lower 16 form an imaginary part. There is one data input (IN) to the register and one output (OUT). Both have the same width of 32 bits. The contents of the register are shifted on a rising edge of CLK. The feedback register contains a feedback loop that connects output of the register with its input. The loop is opened when FEN=’1’.

Spatial Filter Coefficients Memory (4)

In this project a ROM memory will be developed. It is used to store spatial filter coefficients.

Table 3 Interface of spatial filter coefficients memory.

Input
ADDR	10 bits
OE*	1 bit
Output
DATA_OUT	32 bits

The memory contains 729 (addressable space is 1024) memory locations. Each memory cell can store n=32 bit data. The m=11 bit address port (ADDR) is sampled on a falling edge of OE* and the memory contents are exhibited on Data_out port.

Simplified timing diagrams are enclosed in the Appendix.

Matched Filter Coefficients Memory (13)

In this project a read-only memory (ROM) will be developed. It is used to store dispersive filter (matched filter) coefficients.

Table 4 Interface of matched filter coefficients memory.

Input
ADDR	11 bits
OE*	1 bit
CE*	1 bit
Output
DATA_OUT	32 bits

The memory contains 2048 memory locations. Each memory cell can store n=32 bits data. The m=11 bit address port is sampled on a falling edge of OE* and one clock cycle later the memory contents are exhibited on Data_out port.

Simplified timing diagrams are enclosed in the Appendix.

Template Memory (11)

The purpose of this project is to develop a template memory. Template memory is a programmable memory used to store enrollment data. (read-only memory can be used instead).

Table 5 Interface of Template Memory.

Input
CLK	1 bit
ADDR	12 bits
Output
DOUT	16 bit

The memory contains 4096 memory locations. Each memory cell can store 16 bits of information. Each image requires 6144 bits of memory for the enrollment. It means that up to 10 fingerprint images can be enrolled and stored in this memory. It is a very modest number considering the fact that it is required to have at least a few fingerprint images per enrolled finger. The small memory size of 8192 bytes has been chosen in order to increase the speed of testing and verification of the system. In the future, however, larger external memory will be used. The template is a vector of 1 bit complex points, so each of memory locations contains 8 complex numbers. The memory interface is straightforward. The 12 bit address is sampled on a rising edge of OE* and one clock cycle later the memory contents are exhibited on Data_out port.

Simplified timing diagrams can be found in the Appendix.

Temporary Memory (7)

The purpose of this project is to develop a single port RAM used to store intermediate data. In our application data are spatial-frequency representation of the fingerprint image.

Table 6 Interface of Temporary Memory.

Input
OE*	1 bit
ADDR	12 bit
WE*	1 bit
DATA_IN	32 bit
Output
DATA_OUT	32 bit

This RAM memory can hold 3072 32 bit numbers (addressable space 4096 memory locations). 32-bit data is read from the memory on the falling edge of OE*, and is written into memory on the falling edge of WE*. During writing the OE* should be ‘1’, and CE* should be ‘0’. Temporary memory serves as an intermediate storage for data produced by the FFT module.

Simplified timing diagrams can be found in the Appendix.

Flash/ EEPROM Parallel Interface (10a)

The purpose of this project is to develop an interface to a programmable memory (EEPROM).

Table 7 EEPROM interface.

Input
CLK	1 bit
PROG	1 bit
READ	1 bit
RESET	1 bit
DATA_IN	16 bit
Output
DATA_OUT	2 bit
ADDR	17 bit
PROG_DONE	1 bit
OE*	1 bit
CE*	1 bit
WE*	1 bit
Input/ output
Data	16 bit

The EEPROM memory interface provides necessary control signals to read from and to write to EEPROM memory. The EEPROM memory is an external storage for enrollment data and maintains valid data when the system power is down. It allows storing larger numbers of templates than the internal system memory but unfortunately it is much slower. Read/ write operations on EEPROM usually require from 20 ns – 250 ns. The EEPROM interface assures 0 latency accesses by reading data ahead and buffering them. The example interface has been shown above.

The interface to the memory (the left side of the block diagram) provides read and write functionality to EEPROM. Timing of the signals should agree with a Flash/ EEPROM memory documentation; simplified timing diagrams are shown below (refer also to AT49BV1024A at www.atmel.com).

The remaining signals are interfacing with the system: the data_out carries template data from the EEPROM, the data_in is used during the EEPROM programming mode (system generates 16 bit template data and the memory interface programs it into EEPROM).

READ=’1’ (1 clock cycle long pulse generated by the system) indicates that on every following rising edge of the system clock the data_out has to contain a valid data. 16 bit data word from EEPROM should be divided into pairs (from MSB on the right to LSB on the left) and sent to data_out, 1 pair per clock cycle.

PROG=’1’ turns the memory programming mode on (design of the programming mode is up to the team; it should be consistent with AT49BV1024A datasheet). PROG_DONE indicates that the 16 bit word has been written into the memory and system can write another one to the EEPROM interface.

RESET=’1’ should be used to initiate the internal registers of EEPROM interaface.

CLK is a system clock.

The memory interface should be designed assuming 100 MHz system clock. The EEPROM read operation takes 45ns.

2-D to 1-D converter (5)

The purpose of this assignment is to develop a memory interface that converts 2-D array coordinates into linear memory address space.

Table 8 Interface of 2-D to 1-D converter.

Input
COL	7 bit
RAW	7 bit
CLK	1 bit
DATA_IN	8 bit
Output
DATA_OUT	8 bit
ADDR	14 bit
CE*	1 bit
OE*	1 bit

The fingerprint image is represented as a 2-D array of pixel data. In our system it is written into a linear memory address space. A simple conversion is needed to convert 2-D coordinates into 1-D. The 2-D to 1-D converter allows for addressing linear memory using row and column coordinates, which is useful when a digital image is stored in a digital memory.

Inputs to the converter are two integer numbers (unsigned bit vectors) corresponding to a row and a column number. The output is an integer number (unsigned bit vector) corresponding to a memory address.

COL and ROW are sampled on a rising edge of CLK. On the next rising edge of CLK address is ready and OE can be generated to initiate reading from RAM (see image memory timing diagrams). Once valid data read from memory is present on DATA_IN (see memory access time) it is also displayed on DATA_OUT, which is an input to the spatial filter.

Spatial Filter SM (5)

The purpose of this project is to develop a spatial filter using VHDL. The filter should be able to apply a set of up to 9 spatial filters to a gray scale image (128 x 128 points). The filter should be parameterized; it should allow for variable input vector widths and a variable number of filters.

In image recognition applications spatial filters are used to enhance the quality of images. They can also be used to extract certain features from a fingerprint image.

In our case the spatial filter consists of a convolution kernel, which is a 2-D array of coefficients (here the array is 9 x 9 coefficients).

The fingerprint image (128 x 128 pixels) is stored in a memory, and then it is spatially filtered. The result of the filtering is an array of 64 by 64 points. The mechanism of spatial filtering is shown in Figure 1. It shows a 3 x 3 points convolution kernel instead of 9 x 9, but the principle remains the same. The convolution kernel is moved from left to right over the array representing the image and stops at every second point. After it has completed one row, it goes to the leftmost position and 2 rows down. At every position of the kernel, the filter coefficients are multiplied by the corresponding pixels and summed together. The kernel stops at a total of 4096 uniformly distributed locations in the image and forms a new, modified array of size 64 by 64 points. On the borders of the image, when the kernel extends beyond the image boundaries, the image pixels are assumed to be of black color (denoted by 0). The example convolution kernel used in the system can defined by the following equations:

Equation 0‑1

,where a_ij is a spatial filter coefficient, and the 9 x 9 convolution kernel represents an edge detector.

For more details on image filtering refer to http://www.eas.asu.edu/~karam/2dconvolution/.

Figure 1 Spatial Filtering.

Multipliers (5,10,12)

The purpose of this assignment is to develop a set of pipelined multipliers operating on fixed point integer numbers. The following table represents the multipliers to be developed:

Table 9 Formats of inputs and outputs of the multipliers.

Block No.	InA	InB	Product
(5)	8 bit real positive	16 bit complex signed	16 bit complex signed
(12)	16 bit real signed	16 bit real signed	16 bit complex real
(10)	1 bit complex (sign bit)	16 bit complex signed	16 bit complex signed
(12)	16 bit complex signed	16 bit complex signed	16 bit complex signed

An example block diagram of a complex multiplier has been presented below. Pipelined register have been inserted between multipliers and adders and form two stages of a simple pipeline. The registers should be triggered by a rising edge of the clock.

Appendix

Memory “read” and “write” operations timing diagrams.