Suggested Design Methodologies

VLSI design can be extremely open ended, i.e. the same design can be implemented in a number of different ways. Teams may implement their chosen designs however they like; however the following document provides a rough blueprint to aid in the design process.

SRAM and Dual Port SRAM

SRAM or static ram is named as such because it does not require a routine refreshing in order to maintain a value. As long as the power supply is on, an SRAM cell will hold its value.

Data are stored as voltage levels with the two sides of the flip-flop in opposite voltage configurations, that is C5 will be high while C6 is low and vice versa.

T3 and T4 are known as load transistors. These transistors slow the leakage current so that it is non negligible only during switching. The following cell diagram can be used as the logic portion of the SRAM single cell.

Single Port SRAM

A single SRAM cell is wired to other similar single cells to form an array of single cells. The logic representation of this array is shown in the figure below.

Array of Multiple SRAM cells

Modern RAM arrays are often extremely large. This indicates that the space taken by each individual cell is extremely important. Not only the size of the cell but also the space between each cell should be minimized. In order to minimize space between the cells, it is necessary that the cells abut each other on all sides. It is easier to accomplish this by, creating an abuttable physical layout of a single cell, rather than try to connect multiple cells together in the schematic as in the figure above. The following figure shows an SRAM layout that is abuttable. It is recommended to use this layout, but actually any layout that can correctly abut on all four sides is satisfactory.

SRAM Physical Layout

The Dual Port SRAM is an extremely useful version of the traditional SRAM cell. The Dual Port SRAM can be simultaneously accessed through both ports. This can significantly decrease the time spent accessing memory. One commonly used design tactic is to access one port using a clk, and access the second port using the inverse of that clk. Using this method there will be no access confliction; as long as setup and hold times for the memory are met.

The following cell is one possible logical implementation of a Dual Port SRAM cell.

Dual Port SRAM Cell

The SRAM architecture is comprised of a memory array, and multiplexing system, used to address specific locations within the array. The example memory array shown below is a 64X64 cell array. This means that it consists of 4096 single memory cells.

SRAM Architecture

The SRAM architecture shown above should work as follows. Row addresses A0 to A5 select the word line, the column addresses A6 to A11 select the bit line pairs to access the correct bit in the memory array. In a read operation this bit is read out onto the bit lines, onto the data bus, through the sense amplifier, and through the 3-state output buffer.

For a write operation, the row and column address buffers and decoders again select the proper word line and bit line pairs. The data on the Data-in pin passes through the three-state input buffers the data bus and is written into the correct location in memory array over the selected bit lines. The Read-Write control buffer controls whether the read or write is selected on the Data-in and Data-out pins.

A sense amplifier is used to sense the difference between the two signals of the bit pair. It is desirable that the sense amplifier be fast, small and have a high degree of stability. A simple inverter can be used as a sense amplifier as shown below.

Inverter as Sense Amplifier

Differential sense amplifiers can also be used for speed since they can sense and amplify a very small difference between two signals. A PMOS sense amplifier is shown below.

Differential Sense Amplifier

DRAM

DRAM is considered “dynamic” because of the need to refresh cell contents periodically. Refreshing data consists of refreshing it to the original 0 or 1 value originally stored in that cell. The figure below shows a three transistor dynamic cell.

Three Transistor Dynamic Cell

This three transistor dynamic cell has two control and two I/O lines. Its separate read and write select lines make it relatively fast, but the four lines with their additional contacts to every cell occupy area making it larger.

The one transistor cell has become the standard dynamic ram cell. With only one transistor and a capacitor, it has the lowest component count and hence smallest chip size of all the dynamic cells. It has one read/write control line and one bit line. It is operated by the row decoder-driver turning on the word line, which controls the gate of the transistor.

One Transistor Dynamic Cell

The figure below shows a NEC, 1mb DRAM organized as 1048576 words X 1b.

NEC 1mb DRAM

Two inputs of the above device are row address strobe RAS and column address strobe CAS (or chip select CS). In addition to reading row addresses A0-A9, selecting the relevant word line and activating the sense amplifiers for the read and write operations, the RAS input also refreshes the 2048 b selected by row addressing circuitry. The CAS input latches in the column address and connects the chips internal i/o bus to the sense amplifiers activated by the RAS clock thereby executing data input or output operations. This device features an address multiplexing, in which an address is divided into two parts, the upper ten bits and the lower ten bits. The row address is latched into the memory at the falling edge of the RAS clock. After an internal timing delay, the column address input circuits become active. Flow-through latches for column addresses are enabled, and the column begins to propagate through the latches to the column decoders. A column address is held in the latches by the falling edge of CAS. The read and write cycles are executed by activating the RAS and CAS or CS inputs and controlling WE. An early write cycle is executed if WE is activated before the falling edge of CAS or CS during a write cycle and a late read cycle is executed if the WE input is activated later. Refreshing is performed by a sense amplifier. All 512 rows must be refreshed within any 8 ms period.

ROM

ROM arrays contain only a single transistor per bit whose state is hardware preprogrammed during the wafer fabrication process and maintained indefinitely without the application of voltage.

The image below shows the NOR array ROM. The NOR array ROM. The NOR array includes a bit line contact for every cell.

NOR ROM Array

The other type of ROM array is the NAND array. The NAND array is a serial structure with only one bit line, hence it is smaller and more cost effective than the NOR array.

NAND ROM Array

Serial Shift Register/ SAM

Shift registers are memory architectures through which data are transferred in and out serially. Registers can be either MOS or CCD. Similar to memory MOS registers can be either static or dynamic. A single static cell is shown below.

Static SAM Cell

The dynamic SAM cell is shown below. The main difference between the Static SAM Cell and the dynamic SAM cell is the lack of transistor T7 in the dynamic cell. T7 is used to hold charge so that the cells do not require refreshing. Dynamic shift registers are smaller and more cost effective.

Dynamic SAM Cell

Data are transferred from cell to cell by the sequential operation of the clocks.