|
№ |
Date |
Topic & Reading Assignment |
Homework/Lab Assignment |
Comment |
|
1 |
Aug.31 |
Getting
Started
Course
Organization (Dr. Rucinska) |
|
Europe |
|
2 |
Sept. 2 |
CAD Environment (Frank Hludik),
Page 1-22,
Tutorial1,
Tutorial2 |
|
Europe |
|
3 |
Sept. 7 |
Lab Overview
(Shibli), Page 23 - 66 |
Lab Exercise
One Assigned |
Europe |
|
4 |
Sept. 9 |
Project
Overview (Corey),
Chapter 8. Design Methodology and Tools |
|
Europe |
|
5 |
Sept. 14 |
VHDL/DSP/DES/Communication (Jakub/Corey)
|
Lab Exercise Two
Assigned |
|
|
6 |
Sept. 16 |
VLSI Philosophy,
Chapter 2. MOS Tarnsistor Theory, Page 67 - 108 |
Lab #1 Due |
|
|
7 |
Sept. 21 |
Review of nMOS
Fundamentals |
Lab Exercise
Three Assigned,
|
|
|
8 |
Sept. 23 |
Student Project
Proposal |
Lab #2 Due, Homework #1
Assigned |
|
|
9 |
Sept. 28 |
Review of CMOS
Fundamentals |
|
|
|
10 |
Sept. 30 |
Labs and
Project Review (Corey/Jakub) |
Lab #3 Due |
SwaNH Conference |
|
11 |
Oct.5 |
Logic Design, Chapter
6.
Combinational
Circuit Design, Page 319 – 378, Chapter 7. Sequential
Circuit Design, Page 383 - 475 |
Lab Exercise
Four Assigned,
Homework #1 Due |
Trade Mission |
|
12 |
Oct.7 |
Logic Design (Continued) |
Homework #2 Assigned |
Trade Mission |
|
13 |
Oct.12 |
Design Rules, Page 125
- 136 |
|
|
|
14 |
Oct.14 |
Design Rules (Continued) |
Lab #4 Due |
|
|
15 |
Oct. 19 |
Simple Layout Examples |
Homework #2 Due |
|
|
16 |
Oct. 21 |
Preliminary
Design Review |
Reverse Engineering
Problem Assigned |
|
|
17 |
Oct. 26 |
System Design, Chapter
10. Datapath Subsystems |
Lab Exercise
Five Assigned |
|
|
18 |
Oct. 28 |
System Design (Continued) |
|
|
|
19 |
Nov. 2 |
Floorplanning
|
|
|
|
20 |
Nov. 4 |
Performance
Characterization, Chapter 4. Circuit Characterization
and Performance Estimation |
Reverse Engineering
Problem Due |
|
|
21 |
Nov. 9 |
Performance
Characterization (Continued) |
Lab #5 Due
|
|
|
22 |
Nov. 11 |
Project Review
(Corey/Jakub) |
|
Tunnel Conference |
|
23 |
Nov. 16 |
Scaling, Page 239 - 266 |
|
|
|
24 |
Nov. 18 |
Critical Design
Review |
|
|
|
25 |
Nov. 23 |
Manufacturing, Chapter
3. CMOS Processing Technology |
|
|
|
26 |
Nov. 25 |
Thanskgiving |
- |
- |
|
27 |
Nov. 30 |
« From Sand to
Circuit « Video |
|
|
|
28 |
Dec. 2 |
Reliability, Testing, and
Testability, Chapter 9. Testing and Verification |
|
|
|
29 |
Dec. 7 |
Trip to BAE
Systems, leaving UNH @ 8 :00 am |
|
|
|
30 |
Dec. 9 |
Boundary Scan, Page 609
- 636 |
|
|
|
31 |
Dec.13 |
Final Design
Review, Course
Evaluation |
|
Reading Day |
